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L4970A 10a switching regulator 10a output current 5.1v to 40v output voltage range 0 to 90% duty cycle range internal feed-forward line regula- tion internal current limiting precise 5.1v 2% on chip reference reset and power fail functions soft start input/output sync pin under voltage lock out with hys- teretic turn-on pwm latch for single pulse per pe- riod very high efficiency switching frequency up to 500khz thermal shutdown continuous mode operation description the L4970A is a stepdown monolithic power switching regulator delivering 10a at a voltage variable from 5.1 to 40v. realized with bcd mixed technology, the device uses a dmos output transistor to obtain very high efficiency and very fast switching times. features of the L4970A include reset and power fail for mi- croprocessors, feed forward line regulation, soft start, limiting current and thermal protection. the device is mounted in a 15-lead multiwatt plastic power package and requires few external compo- nents. efficient operation at switching frequencies up to 500khz allows reduction in the size and cost of external filter components. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change withou t notice. june 2000 ? block diagram multiwatt15v ordering number: L4970A multipower bcd technology 1/21
pin connection (top view) absolute maximum ratings symbol parameter value unit v 9 input voltage 55 v v 9 input operating voltage 50 v v 7 output dc voltage output peak voltage at t = 0.1 m s f = 200khz -1 -7 v v i 7 maximum output current internally limited v 6 bootstrap voltage bootstrap operating voltage 65 v 9 + 15 v v v 3 , v 12 input voltage at pins 3, 12 12 v v 4 reset output voltage 50 v i 4 reset output sink current 50 ma v 5 , v 10, v 11, v 13 input voltage at pin 5, 10, 11, 13 7 v i 5 reset delay sink current 30 ma i 10 error amplifier output sink current 1 a i 12 soft start sink current 30 ma p tot total power dissipation at t case < 120c 30 w t j , t stg junction and storage temperature -40 to 150 c thermal data symbol parameter value unit r th j-case r th j-amb thermal resistance junction-case max thermal resistance junction-ambient max 1 35 c/w c/w L4970A 2/21
circuit operation (refer to the block dia- gram) the L4970A is a 10a monolithic stepdown switching regulator working in continuous mode realized in the new bcd technology. this technology allows the in- tegration of isolated vertical dmos power transistors plus mixed cmos/bipolar transistors. the device can deliver 10a at an output voltage adjustable from 5.1v to 40v, and contains diag- nostic and control functions that make it particu- larly suitable for microprocessor based systems. block diagram the block diagram shows the dmos power tran- sistor and the pwm control loop. integrated func- tions include a reference voltage trimmed to 5.1v 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. the reset and power fail circuit provides an output signal for a microprocessor in- dicating the status of the system. device turn on is around 11v with a typical 1v hysteresis, this threshold provides a correct volt- age for the driving stage of the dmos gate and the hysteresis prevents instabilities. an external bootstrap capacitor charged to 12v by an internal voltage reference is needed to pro- vide correct gate drive to the power dmos. the driving circuit is able to source and sink peak cur- rents of around 0.5a to the gate of the dmos transistor. a typical switching time of the current in the dmos transistor is 50ns. due to the fast commutation switching frequencies up to 500khz are possible. the pwm control loop consists of a sawtooth os- cillator, error amplifier, comparator, latch and the output stage. an error signal is produced by com- paring the output voltage with the precise 5.1v 2% on chip reference. this error signal is then compared with the sawtooth oscillator, in order to generate a fixed frequency pulse width modulated drive for the output stage. a pwm latch is in- cluded to eliminate multiple pulsing within a pe- riod even in noisy environments. the gain and pin functions n o name function 1 oscillator r osc . external resistor connected to ground determines the constant charging current of c osc . 2 oscillator c osc . external capacitor connected to ground determines (with r osc ) the switching frequency. 3 reset input input of power fail circuit. the threshold is 5.1v. it may be connected via a divider to the input for power fail function. it must be connected to the pin 14 an external 30k w resistor when power fail signal not required. 4 reset out open collector reset/power fail signal output. this output is high when the supply and the output voltages are safe. 5 reset delay a c d capacitor connected between this terminal and ground determines the reset signal delay time. 6 bootstrap a c boot capacitor connected between this terminal and the output allows to drive properly the internal d-mos transistor. 7 output regulator output. 8 ground common ground terminal 9 supply voltage unregulated input voltage. 10 frequency compensation a series rc network connected between this terminal and ground determines the regulation loop gain characteristics. 11 feedback input the feedback terminal of the regulation loop. the output is connected directly to this terminal for 5.1v operation; it is connected via a divider for higher voltages. 12 soft start soft start time constant. a capacitor is connected between thi sterminal and ground to define the soft start time constant. 13 sync input multiple L4970A are synchronized by connecting pin 13 inputs together or via an external syncr. pulse. 14 v ref 5.1v v ref device reference voltage. 15 v start internal start-up circuit to drive the power stage. L4970A 3/21
figure 1: feedforward waveform figure 3: limiting current function figure 2: soft start function L4970A 4/21
stability of the loop can be adjusted by an exter- nal rc network connected to the output of the er- ror amplifier. a voltage feedforward control has been added to the oscillator, this maintains supe- rior line regulation over a wide input voltage range. closing the loop directly gives an output voltage of 5.1v, higher voltages are obtained by inserting a voltage divider. at turn on output overcurrents are prevented by the soft start function (fig. 2). the error amplifier is initially clamped by an external capacitor css and allowed to rise linearly under the charge of an in- ternal constant current source. output overload protection is provided by a cur- rent limit circuit (fig. 3). the load current is sensed by an internal metal resistor connected to a com- parator. when the load current exceeds a preset threshold the output of the comparator sets a flip flop which turns off the power dmos. the next clock pulse, from an internal 40khz oscillator will reset the flip flop and the power dmos will again conduct. this current protection method, ensures a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40khz. the reset and power fail circuitry (fig 4) gener- ates an output signal when the supply voltage ex- ceeds a threshold programmed by an external voltage divider. the reset signal, is generated with a delay time programmed by an external ca- pacitor on the delay pin. when the supply voltage falls below the threshold or the output voltage goes below 5v the reset output goes low immedi- ately. the reset output is an open collector-drain. fig 4a shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5v. fig 4b shows the case when the output is 5.1v but the supply voltage is not yet higher than the fixed threshold. the thermal protection disables circuit operation when the junction temperature reaches about 150 c and has an hysterysis to prevent unstable conditions. figure 4: reset and power fail functions. a b L4970A 5/21
electrical characteristics (refer to the test circuit, t j = 25 c, v i = 35v, r 4 = 16k w , c 9 = 2.2nf, f sw = 200khz typ, unless otherwise specified) dynamic characteristics symbol parameter test condition min. typ. max. unit fig. v i input voltage range (pin 9) v o = v ref to 40v i o = 10a 15 50 v 5 v o output votage v i = 15v to 50v i o = 5a; v o = v re f 5 5.1 5.2 v 5 d v o line regulation v i = 15v to 50v i o = 5a; v o = v re f 12 30 mv 5 d v o load regulation v o = v ref i o = 3a to 6a i o = 2a to 10a 10 20 30 50 mv mv 5 v d dropout voltage between pin 9 and 7 i o = 5a i o = 10a 0.55 1.1 0.8 1.6 v v 5 i 7l max. limiting current v i = 15 to 50v 11 13 15 a 5 h efficiency i o = 5a v o = v ref v o = 12v 80 85 92 % % 5 i o = 10a v o = v ref v o = 12v 75 80 87 % % 5 svr supply voltage ripple reject. v i = 2vrms; i o = 5a f = 100hz; v o = v ref 56 60 db 5 f switching frequency 180 200 220 khz 5 d f d v i voltage stability of swiching frequency v i = 15v to 45v 2 6 % 5 d f t j temperature stability of swiching frequency t j = 0 to 125 c1%5 f max maximum operating switching frequency v o = v ref ; r 4 = 10k w i o = 10a; c 9 = 1nf 500 khz 5 v ref section (pin 14) symbol parameter test condition min. typ. max. unit fig. v 14 reference voltage 5 5.1 5.2 v 7 d v 14 line regulation v i = 15v to 50v 10 25 mv 7 d v 14 load regulation i 14 = 0 to 1ma 20 40 mv 7 d v 14 d t average temperature coefficient reference voltage t j = 0 c to 125 c 0.4 mv/ c7 i 14 short short circuit current limit v 14 = 0 70 ma 7 v start section (pin 15) symbol parameter test condition min. typ. max. unit fig. v 15 reference voltage 11.4 12 12.6 v 7 d v 15 line regulation v i = 15 to 50v 0.6 1.4 v 7 d v 15 load regulation i 15 = 0 to 1ma 50 200 mv 7 i 15 short short circuit current limit v 15 = 0v 80 ma 7 L4970A 6/21
electrical characteristics (continued) dc characteristics symbol parameter test condition min. typ. max. unit fig. v 9on turn-on threshold 10 11 12 v 7a v 9 hyst turn-off hysteresys 1 v 7a i 9q quiescent current v 12 = 0; s1 = d 13 19 ma 7a i 9oq operating supply current v 12 = 0; s1 = c; s2 = b 16 23 ma 7a i 7l out leak current v i = 55v; s3 = a; v 12 = 0 2 ma 7a soft start symbol parameter test condition min. typ. max. unit fig. i 12 soft start source current v 12 = 3v; v 11 = 0v 70 100 130 m a7b v 12 output saturation voltage i 12 = 20ma; v 9 = 10v i 12 = 200 m a; v 9 = 10v 1 0.7 v v 7b 7b error amplifier symbol parameter test condition min. typ. max. unit fig. v 10h high level out voltage i 10 = -100 m a; s1 = c v 11 = 4.7v 6v7c v 10l low level out voltage i 10 = +100 m a; s1 = c v 11 = 5.3v; 1.2 v 7c i 10h source output current v 10 = 1v; s1 = e v 11 = 4.7v 100 150 m a7c i 10l sink output current v 10 = 6v; s1 = d v 11 = 5.3v 100 150 m a7c i 11 input bias current r s = 10k w 0.4 3 m aC g v dc open loop gain v vcm = 4v; r s = 10 w 60 db C svr supply voltage rejection 15 < v i < 50v; r s = 10 w 60 80 db C v os input offset voltage r s = 50 w 210mvC ramp generator (pin 2) symbol parameter test condition min. typ. max. unit fig. v 2 ramp valley s1 = c; s2 = b 1.2 1.5 v 7a v 2 ramp peak s1 = c; v i = 15v s2 = b; v i = 45v 2.5 5.5 v v 7a 7a i 2 min. ramp current s1 = a; i 1 = 100 m a 270 300 m a7a i 2 max. ramp current s1 = a; i1 = 1ma 2.4 2.7 ma 7a sync function (pin 13) symbol parameter test condition min. typ. max. unit fig. v 13 low input voltage v i = 15v to 50v; v 12 = 0; s1 = c; s2 = b; s4 = b C0.3 0.9 v 7a v 13 high input voltage v 12 = 0; s1 = c; s2 = b; s4 = b 3.5 5.5 v 7a i 13l sync input current with low input voltage v 13 = v 2 = 0.9v; s4 = a; s1 = c; s2 = b 0.4 ma 7a i 13h input current with high input voltage v 13 = 3.5v; s4 = a; s1 = c; s2 = b 2ma7a v 13 output amplitude 4 5 v C t w output pulse width v thr = 2.5v 0.3 0.5 0.8 m sC L4970A 7/21
electrical characteristics (continued) reset and power fail functions symbol parameter test condition min. typ. max. unit fig. v 11r rising threshold voltage (pin 11) v i = 15 to 50v v 3 = 5.3v v ref C120 v ref C100 v ref C80 v mv 7d v 11f falling threshold voltage (pin 11) vi = 15 to 50v v 3 = 5.3v 4.77 v ref C200 v ref C160 v mv 7d v 5h delay high threshold voltage v i = 15 to 50v v 14 = v 11 v 3 = 5.3v 4.95 5.1 5.25 v 7d v 5l delay low threshold voltage vi = 15 to 50v v 14 = v 11 v 3 = 5.3v 1 1.1 1.2 v 7d Ci 5so delay source current v 3 = 5.3v; v 5 = 3v 40 60 80 m a7d i 5si delay sink current v 3 = 4.7v; v 5 = 3v 10 ma 7d v 4s out saturation voltage i 4 = 15ma; s1 = b v 3 = 4.7v 0.4 v 7d i 4 output leak current v 4 = 50v; s1 = a v 3 = 5.3v 100 m a7d v 3r rising threshold voltage v 11 = v 14 4.95 5.1 5.25 v 7d v 3h hysteresys 0.4 0.5 0.6 v 7d i 3 input bias current 1 3 m a7d figure 5: test and evaluation board circuit typical performances (using evaluation board) : n = 83% (v i = 35v ; v o = v ref ; i o = 10a ; f sw = 200khz) v o ripple = 30mv (at 10a) with output filter capacitor esr 60m w line regulation = 5mv (v i = 15 to 50v) load regulation = 15mv (i o = 2 to 10a) for component values, refer to test circuit part list. L4970A 8/21
parts list r 1 = 30k w c 1 , c 2 = 3300 m f 63v l eyf (roe r 2 = 10k w c 3 , c 4 , c 5 , c 6 = 2.2 m f r 3 = 15k w c 7 = 390pf film r 4 = 16k w c 8 = 22nf mkt 1817 (ero) r 5 = 22 w 0,5w r 6 = 4k7 c 9 = 2.2nf kp1830 r 7 = 10 w c 10 = 220nf mkt r 8 = see tab. a c 11 = 2.2nf mp1830 r 9 = option **c 12 , c 13 , c 14 = 220 m f 40v l ekr r 10 = 4k7 c 15 = 1 m f film r 11 = 10 w d1 = mbr 1560ct (or 16a/60v or equivalent) l1 = 40 m h core 58071 magnetics 27 turns ? 1,3mm (awg 16) cogema 949178 * 2 capacitors in parallel to increase input rms current capab ility ** 3 capacitors in parallel to reduce total output esr table b suggested bootstrap capacitors operating frequency bootstrap cap.c10 f = 20khz 3 680nf f = 50khz 3 470nf f = 100khz 3 330nf f = 200khz 3 220nf f = 500khz 3 100nf figure 6a: p.c. board (components side) and components layout of figure 5 (1:1 scale). table a v 0 r 9 r 7 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2kw 9.1k w 12k w 18k w L4970A 9/21
figure 7: dc test circuits figure 6b: p.c. board (back side) and components layout of the circuit of fig. 5. (1:1 scale) L4970A 10/21
figure 7a figure 7b L4970A 11/21
figure 7c figure 7d L4970A 12/21
figure 8: quiescent drain current vs. supply voltage (0% duty cycle - see fig. 7a). figure 10: quiescent drain current vs. duty cycle figure 12: reference voltage (pin 14) vs. junction temperature (see fig. 7) figure 9: quiescent drain current vs. junction temperature (0% duty cycle). figure 11: reference voltage (pin14) vs. v i (see fig. 7) figure 13: reference voltage (pin15) vs. v i (see fig. 7) L4970A 13/21
figure 14: reference voltage (pin 15) vs. junction temperature (see fig. 7) figure 16: switching frequency vs. input voltage (see fig. 5) figure 18: switching frequency vs. r4 (see fig. 5) figure 15: reference voltage 5.1v (pin 14) supply voltage ripple rejection vs. frequency figure 17: switching frequency vs. junction temperature (see fig 5) figure 19: max. duty cycle vs. frequency L4970A 14/21
figure 20: supply voltage ripple rejection vs. frequency (see fig. 5) figure 22: load transient response (see fig. 5) figure 24: dropout voltage between pin 9 and pin 7 vs. junction temperature figure 21: line transient response (see fig. 5) figure 23: dropout voltage between pin 9 and pin 7 vs. current at pin 7 figure 25: power dissipation (device only) vs. input voltage L4970A 15/21
figure 26: power dissipation (device only) vs. output voltage figure 28: efficiency vs. output current figure 30: efficiency vs. output voltage figure 27: heatsink used to derive the devices power dissipation r th - heatsink = t case - t amb p d figure 29: efficiency vs. output voltage figure 31: open loop frequency and phase response of error amplifier (see fig.7c) L4970A 16/21
figure 32: power dissipation derating curve figure 33: a5.1v/12v multiple supply. note the synchronization between the L4970A and the l4974a L4970A 17/21
figure 34: 5.1v / 10a low cost application figure 35: 10a switching regulator, adjustable from 0v to 25v. L4970A 18/21
figure 36: L4970As sync. example L4970A 19/21
multiwatt15 v dim. mm inch min. typ. max. min. typ. max. a 5 0.197 b 2.65 0.104 c 1.6 0.063 d 1 0.039 e 0.49 0.55 0.019 0.022 f 0.66 0.75 0.026 0.030 g 1.02 1.27 1.52 0.040 0.050 0.060 g1 17.53 17.78 18.03 0.690 0.700 0.710 h1 19.6 0.772 h2 20.2 0.795 l 21.9 22.2 22.5 0.862 0.874 0.886 l1 21.7 22.1 22.5 0.854 0.870 0.886 l2 17.65 18.1 0.695 0.713 l3 17.25 17.5 17.75 0.679 0.689 0.699 l4 10.3 10.7 10.9 0.406 0.421 0.429 l7 2.65 2.9 0.104 0.114 m 4.25 4.55 4.85 0.167 0.179 0.191 m1 4.63 5.08 5.53 0.182 0.200 0.218 s 1.9 2.6 0.075 0.102 s1 1.9 2.6 0.075 0.102 dia1 3.65 3.85 0.144 0.152 outline and mechanical data L4970A 20/21
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com L4970A 21/21

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